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Altera_Forum
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9 years ago

PCIe Hard IP build error

i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! -...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

thanks for your help,i solve the problem now,it's all because of the "pin_perst" pin ,each Hard IP core should have a single "pin_perst" ,but in my original project,the two PCIe core share a pin_perst signal ,that's the problem.