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Honored Contributor
Honored ContributorPCIe Hard IP build error
i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! -...
Altera_ForumHonored Contributor
Honored Contributorthe device is Cycone V 5cGXFC7D6F31C7ES,my project use two Avalon-MM Cyclone V hard IP for PCI-e,and all devices are native endpoint X1,the pin pcie1_rx_p is the RX channel in PCIe,i set it to PIN_R2 (GXB_L2) .
