Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorPCIe Hard IP build error
i add two PCIe hard IP in my project(the FPGA device support two PCIe core),but Quartus show the error as follow, i am new to FPGA,could anybody help me solve the problem ? thanks very much! -...
Altera_ForumHonored Contributor
Honored ContributorWe don't have crystal balls.
What device are you using? What settings are you using for your hard-ip core? What pins are you constraining the transceivers and clocks to?
