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ZVere's avatar
ZVere
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4 years ago

PCIe dma trasfer optimization

Hello, We have an implementation of an FPGA device (intel stratix5) connected to Broadwell-D (1559 ) using x8 PCIe GenIII interface. The FPGA consists 8 input channels of aprox.250MB/s (total aggr...
Harris's avatar
Harris
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4 years ago

Hi ZVere,

1, I guess the multiple channel DMA is designed by yourself, I know nothing about your design, so I don't have any suggestion for your design.

2, I suggest you try polling scheme instead of interrupt scheme. I suspect so many interrupts might not be handled by system timely. It might be the reason of low performance.

3, You also can use Signaltap to capture some signals and check the timing relation to help analyze the issue.

Thanks.

Harris

ZVere's avatar
ZVere
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4 years ago

Hi Harris,

I must use interrupts.

We are not sure the DMA design in FPGA is implemented in the best way.

I wonder how a standard (Melanox) 40Gb ethernet card is working compared to our design.

Thank you,

Zvika

  • Harris's avatar
    Harris
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    4 years ago

    Hi Zvika ,

    I'm sorry, I know nothing about Melanox ethernet card. And I guess the DMA design is implemented by yourselves. I can't provide any other suggestion to you. Thanks.

    BR/Harris