PCI Express HARD IP implementation using STRATIX IV FPGA

hii,

please anyone help me for the above query.

hii,

actually in qsys, i am unable to find 64-bit parallel i/o.. this might be silly question for you but i am unable to find. but in megawizard plug-in manager, its available. so please guide me.

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hii, actually i am buildind a root port not an end point. its a pcie x1 gen2 design.

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IT does not matter if it is a root port or an endpoint. In the end the problem is the same. You have to make sure you use the correct file for simulation and the correct file for synthesis. The main .v (or vhd) that shows up in the directory has a few hundred ports that apply only in simulation. In the examples <...>_examples/chaining_dma/...._top.v file you see the top level file instantiated in side another block and that one is the top that the example uses. You will see all the simulation only pins floating.

My question to you is if you made sure those simulation only ports (txdatak, txelecidle, etc) are not being ported out. If they are you need to remove them from the ports. The actual IP will have only the lanes (rx_in/tx_out) a few reference clocks and some overhead signals that need to go to the pins. The other side, that talks to your application layer, of course will need to be connected internally to whatever you designed.