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Altera_Forum's avatar
Altera_Forum
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13 years ago

pci express dma transfer

hey !!

i´ve got a qsys system similar to that given in the "ip compiler for pci express user guide" on page 328 (picture attached).

on the host pc i´ve got a linux os running. the driver for the pci interface works fine so far, i can write data and read back values on several i/o´s and onchip memory, also an irq can be received at the host pc, so pci express interface is working proper.

anyway, now i want to initiate a dma transfer from onchipmemory to pci but i´m confused which addresses i´ve to write to the configuration register. i´ve tried several variants but wasn´t successful so far.

can anybody give me a short instruction or explain the certain steps to which control registers i´ve to write which value to get a dma transfer working ?!?

thanks for ur help.

greets

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    i want to initiate a dma transfer from onchipmemory to pci but i´m confused which addresses i´ve to write to the configuration register.

    --- Quote End ---

    The DMA controller can only generate Avalon-MM addresses. When you DMA from the on-chip memory to the TXS slave, you'll use an Avalon-MM address that corresponds to the TXS slave.

    In the CRA registers, there will be a register that determines the PCIe address that the TXS slave generates on the PCIe bus. The MSBs of the 64-bit PCIe address will be determined by this register, while the LSBs will be determined from the Avalon-MM address. If you setup a pair of 1MB TXS windows when you configured the PCIe core, then any DMA to the first 1MB of the TXS address range will be translated according to the first CRA translation address, and any DMA to the second 1MB TXS address range will translate via the second CRA register.

    The PCIe address of the target memory is whatever the physical address of memory is. I forget the device driver mapping API call, but it sounds like you know what you are doing at that end. Once you have the PCIe address of the host memory, eg., 0x1234_5678_9abc_0000, then you can program the address modulo 1MB into the CRA register. You would then program the DMA address register with the offset into the 1MB register (the offset is the remainder of the host address after modulo 1MB ), eg., for the host address 0x1234_5678_9abc_0000, the PCIe CRA register gets programmed with the MSBs 0x1234_5678_9ab0_0000, and the Qsys DMA offset into the TXS register is 0xc_0000.

    (I haven't actually done this on the Qsys PCIe core, but this is how most bridges like this work)

    Cheers,

    Dave