Pausing target processor not responding in stratix 2

Here how it goes, previously i mentioned that i can run the program using "on chip memory" and the problem occurs when i add DDR SDRAM. So it seems like i have problem with my DDR SDRAM. I figure out that my problem is caused by my top level module which i wrongly assign one of the signal, "global_reset_n_to_the_ddr_sdram". i had include my top level module for your view.....but i need some explaination based on this problem ?? All the best for all beginers like me... :)

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module system(

// 1) global signals:

clk, reset_n,

// the_ddr_sdram_0

ddr_a, ddr_ba, ddr_cas_n, ddr_cke, clk_to_sdram_n, clk_to_sdram, ddr_cs_n, ddr_dm, ddr_dq, ddr_dqs, ddr_ras_n, ddr_we_n );

// 1) global signals:

input clk; input reset_n;

// DDR SDRAM

// i/o signal

output [12: 0] ddr_a; output [ 1: 0] ddr_ba; output [ 1: 0] ddr_cas_n; output [ 1: 0] ddr_cke; inout [ 1: 0] clk_to_sdram_n; inout [ 1: 0] clk_to_sdram; output [ 1: 0] ddr_cs_n; output [ 1: 0] ddr_dm; inout [15: 0] ddr_dq; inout [ 1: 0 ] ddr_dqs; output [ 1: 0 ] ddr_ras_n; output [ 1: 0 ] ddr_we_n;

//wires wire

ddr_sdram_aux_full_rate_clk_out; wire ddr_sdram_aux_half_rate_clk_out; wire ddr_sdram_phy_clk_out; wire dll_reference_clk_from_the_ddr_sdram; wire [ 5: 0] dqs_delay_ctrl_export_from_the_ddr_sdram; wire local_init_done_from_the_ddr_sdram; wire local_refresh_ack_from_the_ddr_sdram; wire local_wdata_req_from_the_ddr_sdram; wire reset_phy_clk_n_from_the_ddr_sdram; wire global_reset_n_to_the_ddr_sdram;

system_file the_system_file

( //global signals:

.clk (clk), .reset_n (reset_n),

//DDR SDRAM

//wires

.ddr_sdram_aux_full_rate_clk_out (ddr_sdram_aux_full_rate_clk_out), .ddr_sdram_aux_half_rate_clk_out (ddr_sdram_aux_half_rate_clk_out), .ddr_sdram_phy_clk_out (ddr_sdram_phy_clk_out), .dll_reference_clk_from_the_ddr_sdram (dll_reference_clk_from_the_ddr_sdram), .dqs_delay_ctrl_export_from_the_ddr_sdram (dqs_delay_ctrl_export_from_the_ddr_sdram),

//HERE IS THE CHANGES THAT I HAD MADE

// .global_reset_n_to_the_ddr_sdram (global_reset_n_to_the_ddr_sdram),

.global_reset_n_to_the_ddr_sdram (reset_n),

.local_init_done_from_the_ddr_sdram (local_init_done_from_the_ddr_sdram), .local_refresh_ack_from_the_ddr_sdram (local_refresh_ack_from_the_ddr_sdram), .local_wdata_req_from_the_ddr_sdram (local_wdata_req_from_the_ddr_sdram), .reset_phy_clk_n_from_the_ddr_sdram (reset_phy_clk_n_from_the_ddr_sdram),

//io signals

.mem_addr_from_the_ddr_sdram (ddr_a), .mem_ba_from_the_ddr_sdram (ddr_ba), .mem_cas_n_from_the_ddr_sdram (ddr_cas_n), .mem_cke_from_the_ddr_sdram (ddr_cke), .mem_clk_n_to_and_from_the_ddr_sdram (clk_to_sdram_n), .mem_clk_to_and_from_the_ddr_sdram (clk_to_sdram), .mem_cs_n_from_the_ddr_sdram (ddr_cs_n), .mem_dm_from_the_ddr_sdram (ddr_dm), .mem_dq_to_and_from_the_ddr_sdram (ddr_dq), .mem_dqs_to_and_from_the_ddr_sdram (ddr_dqs), .mem_ras_n_from_the_ddr_sdram (ddr_ras_n), .mem_we_n_from_the_ddr_sdram (ddr_we_n) );

endmodule

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