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Altera_Forum
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16 years ago

Pausing target processor not responding in stratix 2

Hi all, Im a new user in FPGA board. Currently i have a problem regarding my project. I able to generate and download my .sof file into my fpga board without any error. Then i also manage to bu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

have you tried with design example provided by altera for Nios II development kit for 2S60 board ?

You can get ready made system from <Nios installation dir>\examples\verilog

Try simple c program with DDR as program memory using this system.