pass generic value to a vhdl file in verilog

Hey !!

Does anybody know how to pass generic values to a vhdl file in verilog ?

I have the following entities and instantiations:

VHDL entity:

entity test_interface is

generic (

IOPORT : in std_logic_vector (15 downto 0)

);

port(

interface_clk : in std_logic;

interface_frame_n : in std_logic;

interface_reset_n : in std_logic;

interface_ad : in std_logic_vector (3 downto 0);

data : out std_logic_vector (7 downto 0)

);

end test_interface;

in my verilog file a instantiate the VHDL entity as follows:

test_interface test_interface(

.interface_clk(clk),

.interface_frame_n(frame_n),

.interface_reset_n(reset_n),

.interface_ad(ad),

.data(data)

);

I want to set the generic value of IOPORT to x"0080"

The interface works fine, but where and how do i place the generic value in verilog code ??

thanks for your help

greets