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Altera_Forum's avatar
Altera_Forum
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14 years ago

parallel lvds outputs

I need to drive an IR led driver at high speed. the driver has multiple channels (6) an all are paralleled in a single enable input. The driver's enable input is lvds but the input capacitance per pi...
Altera_Forum's avatar
Altera_Forum
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14 years ago

LVDS outputs are dfferential current sources with 100 ohm termination at the receiver according to the standard. Capacitive load won't be a problem for the driver but of course limits the link speed.

I never heard about a "LVDS" receiver with multiple 100 pF input capacitance and can't see a reasonable purpose for it. Are you sure about the info?

But definitely not a question related to Altera FPGA anyhow.