Hi Zying,
No update. Unfortunately your previous response has nothing useful to my original questions. Have you or your design team had a chance to review the provided Quartus archive files?
Below is response to your questions:
- Please make sure that you have turn on Enable PHY reconfiguration on the Top-Level Settings tab if you are using xcvr_reconfig. For further information, you may refer link below, Section 4.13. PHY Reconfiguration Interface, 4.13. PHY Reconfiguration Interface (intel.com).
- [Binu] So enabling P-tile Debug tool kit is not enough? This goes back to my original question.
- Please make sure that you have do the pin assignment and please connect all needed. You may refer to the example design under https://cdrdv2.intel.com/v1/dl/getContent/736492 . For further information, you may refer to our page, installer package, https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agf014.html
- [Binu] As mentioned previously in this thread, I have made the clock pin assignment as mentioned in the guide. I am aware of Intel example design and that is the one I updated to enable Debug tool kit. So I am fully aware of the above links and have mentioned my steps clearly. Providing the links again and again is not helpful.
- For the PCIe, did you connect to the host ? are you reboot the host after programming the .sof ?
- [Binu] Yes of course connected to host for checking PCIe link status.
From what you are saying, I don't think you have a solution for my question. That is unless you can clarify with your internal design team.
Regards
Binu
Occasional Contributor
