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Altera_Forum's avatar
Altera_Forum
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9 years ago

output timing setup

Hi everybody,

I'm designing a system based on the Cyclone IVE fpga and I'm a bit confused in setting up output timing constraints.

The FPGA system is generating data on a port Pout, that is clocked with a 50MHz clock (CLKfpga ; 20s period). Such data is read off chip by a device DEVoc, still clocked at 50MHz (CLKoc), that has Tsu of 2.5ns (from data sheet).

In order to be sure to meet the timing requirements, CLKfpga and CLKoc are 180° phase shifted, that means that data on port Pout have a time window of 7.5ns from the rising edge of CLKfpga to become stable before to be latched by CLKoc.

With this in mind I set:

set_max_delay -from [get_clocks CLKfpga] -to [get_ports Pout] 7.5

and indeed I meet the timing requirements.

My questions now are:

1. Should I also use the set_output_delay command to add further timing requirements?

2. How are set_max_delay and set_output_delay timing specifications related?

3. Should I specify a timing requirement for CLKoc?

thanks to anybody who will help me to understand these points.

Gian Nicola

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    “set_max_delay” and “set_min_delay” are meant to define delays directly as the name implies.

    For example it can be used for source synchronous outputs to external device having tSU of 3ns and tH of 1ns and equal data clock delay as follows:

    set_min_delay 1 #so that it does not hit hold window of previous clock edge

    set_max_delay (clk period - 3) #so that it does not hit setup window of next clock edge

    It can also be used as alternative to multicycles e.g a multicycle of 2 for setup implies you can delay maximum upto two clocks(minus setup window) and a multicycle of hold of 1 implies you can delay minimum of 0(plus hold window)

    The “set_output_delay” is unique for outputs and has different definition from just direct delays. For above case it should be:

    set_output_delay -min -1 …

    set_output_delay –max 2 …

    set_input_delay on the other hand is information given to TQ about incoming inputs and can’t be replaced by set_max_delay though you can set direct delays from input pins to their registers.

    set_max_delay and set_min_delay override others (I believe see TQ priorities)