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Honored Contributor
Honored Contributoroutput timing setup
Hi everybody, I'm designing a system based on the Cyclone IVE fpga and I'm a bit confused in setting up output timing constraints. The FPGA system is generating data on a port Pout, that is cloc...
Altera_ForumHonored Contributor
Honored Contributor“set_max_delay” and “set_min_delay” are meant to define delays directly as the name implies.
For example it can be used for source synchronous outputs to external device having tSU of 3ns and tH of 1ns and equal data clock delay as follows: set_min_delay 1 #so that it does not hit hold window of previous clock edge set_max_delay (clk period - 3) #so that it does not hit setup window of next clock edge It can also be used as alternative to multicycles e.g a multicycle of 2 for setup implies you can delay maximum upto two clocks(minus setup window) and a multicycle of hold of 1 implies you can delay minimum of 0(plus hold window) The “set_output_delay” is unique for outputs and has different definition from just direct delays. For above case it should be: set_output_delay -min -1 … set_output_delay –max 2 … set_input_delay on the other hand is information given to TQ about incoming inputs and can’t be replaced by set_max_delay though you can set direct delays from input pins to their registers. set_max_delay and set_min_delay override others (I believe see TQ priorities)
