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The arrow haves ddr3 mem in both hps and fpga fabric sides, i think that surely the video block uses the fpga ddr3 memory.
These example is useful to explore the kernel files and see how it works !!
I designed a expansion board (or cape) that fits perfectly with the nano soc, it includes an adv7123 video dac a wolfson audio codec but i will redesign it for adding a little ddr too(for the fpga side)
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Hi, it is not really necessary at normal resolution, if you wish have full HD or 4HD then a separate memory is better due memory channel bandwidth reduce processor speed too.
Memory of HPS can be accessed from FPGA and FPGA memory controller can be accessed from HPS too.
Which IP did you used for your design and how are they interconnected on QSYS?
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