OSERDES using DDR

Which FPGA family are you referring to? Highest DDR clock frequency is around 400 MHz, correspending to 800 MHz data rate. Higher data rates up to 1600 Mbps are available with Stratix dedicated SERDES.

I'm targeting Stratix V GX. According to the spec sheets, I should be able to drive the SERDES at more than 1.4Gbs (my requirement), but I need this to transmit data on both the positive and negative 700MHz clock edges. I was able to get a version of this working, but only if I don't use the external PLL option. It looks like there may be an issue with the files generated by the Mega Function GUI. You can't change the input clock frequency in the GUI (the drop down box shows this as 100MHz and you can't change this value even if you vary all the other parameters) . Also, a simulation of this MF will not work correctly unless you manually change the input frequency to 700MHz in the VHDL code. Additionally, if you try to use the external PLL option, the GUI does not let you specify either the output data rate or the input clock frequency. I don't see how the SERDES core knows to make the output double data rate (i.e. transmitting data on both clock edges) without these two parameters since the ratio would determine whether you are transmitting SDR or DDR. I posted a service request to Altera Support on this.

Altera Support had me re-install Quartus 11.1 SP2 and it fixed the problem with the GUI not being able to change the 100MHz value.