OpenCores MAC timing contraints

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Hi,

I have several clocks like 'rx_busy_dc_reg' that are not constrainted...

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Those are not clocks; rx_busy_dc_reg and similar are actually registers.

Your problem is that such registers in OpenCores mac have different input and output clocks: you have the main system clock on one side and the mac tx or rx clock on the other.

Since they generally have different frequencies (i.e. 100MHz for main clock and 25MHz for rx/tx clock), you need to apply set_multicycle_path directives to these paths in the .sdc file.