Open drain pin assignment

I don't think you have to go that low. Just saying

someoutput = 1'b0 ? drivenlow ! 1'bz;

should do the trick - but my Verilog is very, very rusty. I do not know how to expand this to a bus in Verilog, but in VHDL it would read something like

for i in bus'RANGE loop

if bus(i) = '0' then

buspin(i) <= '0';

else

buspin(i) <= 'Z';

end if;

end loop;

Does that answer your question?

Best regards,

Ben