Open Drain MAX3000A

Hello,

the MAX3000A datasheet specifies max. input risetime of 40 ns among recommended operating conditions. You should consider, that the internal logic is really fast compared to HC series. With slow edges, you can easily get doubled clock pulses and similar issues.

It is possible, that circuits as you suggested may work with MAX300a, but I wouldn't expect reliable operation. I would use external gates for signal conditioning.

Regards,

Frank

I thought so, thanks.

In fact, I have to use a PWM signal comming from a simple XOR phase comparator (XOR phase comp. due to noise considerations). After LPF I need 0...9V swing so I can use one of MAX3000's XOR gate and use 1 externally OC buffer before LPF. I already have some 7406 buffers as level translators in project.

I have one more hardware question:

For a signal conditioner, from sine to logic like in image

http://www.hcv.ro/signal.gif

http://www.hcv.ro/osc.gif

Will work in CPLD or I have to use externally HC00 ? Same question if I have to implement a simple XTAL oscillator (of course, only gates inside CPLD).

Thanks in advance

Edi,

Hello,

MAX3000 can handle up to 5 V input and open drain output voltage. Absolute maximum I/O pin voltage specification is 5.7 V. The intended 9 V would certainly damage the device, you must use an external driver.

Regards,

Frank