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Altera_Forum
Honored Contributor
Honored Contributorone shot and D flip flops
Greetings. What is the advantage of putting one shots (one clock pulse if the D in a flip flop goes high) and basic D flip flops in designs? I see them placed in a lot of designs I look and an...
Altera_ForumHonored Contributor
Honored Contributorusing the outputs of logic/registers as clocks is a general no-no in FPGAs. You CAN do it, but unless you get the "clock" into a clock net you're going to have timing problems.
Its best to use clock enables (and much less complicated and much easier for another engineer to understand.)
