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Altera_Forum
Honored Contributor
Honored ContributorOne Sample Delay Code
I have a 13 bit bus singal with a reference clock, each 13-bit represents a sample sychronized with the rising edge of the reference clock,any idea (vhdl code) on how i can achive 1 sample delay?
Altera_ForumHonored Contributor
Honored ContributorBy inserting a D Flip-Flop (for each bit), with your sample in input and your clock in clock input.
