One clock output pulse from debounce logic

I ditched VHDL long ago so I'll describe this at a high level.

Build a down counter that counts down while the signal you are debouncing is in it's "active" state. Any time the signal bounces back to the non active state then you reset the counter to it's initial value. If the counter hits 0 detect this and drive a signal called "detected" high. Wire "detected" into a rising edge detector to create a one cycle pulse.

In case you haven't built a rising edge detector what you would do is register "detected" and call it ... "detected_d1". Then you create the one cycle pulse like this:

strobe = detected AND (NOT detected_d1) <--- however you write this in VHDL....

If you draw the waveform of this logic you'll see how it works.

So coding it this way you shouldn't even need a statemachine; however, you can still use one to implement the downcounter.