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Altera_Forum's avatar
Altera_Forum
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16 years ago

Onchip Fifo AVST to AVMM and Nios

Hello all,

I have run into an odd problem. I am using the SOPC 8.0 sp1 Onchip fifo.

It is configured to be an 32bit AVst sink and AVMM slave out and is connected to the Nios Data Master in SOPC.

With the above setup i get the Info message bellow:-

Info: fifo_0: The FIFO does not support burst transfers. Enabling burst transfers between the Nios II instruction/data masters and the FIFO may lead to undesirable effects.

I have no idea how to disable burst transfers in NIOS, Is there away to do that? Can I ignore the above info message?

Here is the ODD behavior:-

The code below works fine, this snippet of code is reading the on chip FIFO with a IORD command.

for( i = 0; i < 100; i++ )

{

Offset =IORD(FIFO_0_BASE,0);

}

The code below seems to stall,this snippet of code is using pointer dereferencing.

alt_u32 volatile *source_ptr; // declare a pointer *source_ptr

source_ptr = (alt_u32*) FIFO_0_BASE; //Initialiaze pointer address to Fifo_0 addr

for( i = 0; i < 100; i++ ) //run loop

{

Offset =*source_ptr; //Store the data read in address source_ptr and put it in Offset

}

Please can some one tell me why is the second snippet causing my fifo not to give any data out? When observing the signals in signal tap Nios Does not even attempt to read the interface even once.

Please help

regards nadeem

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2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    volatile does _not_ bypass the cache. ORing bit 31 into your pointer would. If all you're doing is this sort of access, you'll never be using burst.

    Cheers,

    - Ura
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I don't know how the FIFO works but if it asserts a waitrequest when there is no data available, that could be causing you to hang. Yeah I would assert bit 31 of your pointer and try it.

    Jake