on chip memory on system

--- Quote Start ---

Post something for us to look at...

--- Quote End ---

module main(

input CLOCK_50,

input [0:0] KEY,

inout [15:0] SRAM_DQ,

output [19:0] SRAM_ADDR,

output SRAM_UB_N,

output SRAM_LB_N,

output SRAM_WE_N,

output SRAM_CE_N,

output SRAM_OE_N

);

main_sys u0 (

.clk_clk (CLOCK_50), // clk.clk

.reset_reset_n (KEY), // reset.reset_n

.sram_0_external_interface_DQ (SRAM_DQ), // sram_0_external_interface.DQ

.sram_0_external_interface_ADDR (SRAM_ADDR), // .ADDR

.sram_0_external_interface_LB_N (SRAM_LB_N), // .LB_N

.sram_0_external_interface_UB_N (SRAM_UB_N), // .UB_N

.sram_0_external_interface_CE_N (SRAM_CE_N), // .CE_N

.sram_0_external_interface_OE_N (SRAM_OE_N), // .OE_N

.sram_0_external_interface_WE_N (SRAM_WE_N) // .WE_N

);

endmodule

when i load software on eclipse nios 2 to board, it has notification "verify failed between address 0x200000 and 0x205517" and then have windown "Downloading ELF Process failed".

Please help me. Thanks!

This is most likely to be a signal integrity issue. Has this hardware ever worked? Is this your own board? There's nothing wrong with the code you've posted.

Cheers,

Alex

I highly doubt Altera's got 2 megs of SRAM on-board, so it sounds like this is on a dev-board external to the FPGA. Read the documentation and make sure you adhere to the setup/hold times and all that. If you ARE using blockram or similar, note that most in- and outputs are registered, which adds to your delay. For example, reading a value from blockram with registered in- and outputs would take 2 clocks before you get the result.

DRAM is a whole different issue :-)

-Mux