Forum Discussion
Altera_Forum
Honored Contributor
8 years agoI highly doubt Altera's got 2 megs of SRAM on-board, so it sounds like this is on a dev-board external to the FPGA. Read the documentation and make sure you adhere to the setup/hold times and all that. If you ARE using blockram or similar, note that most in- and outputs are registered, which adds to your delay. For example, reading a value from blockram with registered in- and outputs would take 2 clocks before you get the result.
DRAM is a whole different issue :-) -Mux