Forum Discussion
New ContributorOn-Chip Lookup Sensitivity Processing on Stratix10, Arria 10
Ok, it looks like the answer here is that you need FEATUREs in your license file in order to do the sensitivity processing. In the end I contacted the sales department, let them know what I wanted to do, and then they sent me a new license that had more FEATUREs in it.
Once you know this is the issue, you can actually see it in one of the user guides. There wasn't anything about it in the Advanced SEU Detecetion IP core guide, nothing in the Error Message Register Unloader IP core guide. However, there's a line in the Fault Injection IP core guide that says,
"The following hardware and software is required to use the Fault Injection Debugger:
- FEATURE line in your Intel FPGA license that enables the Fault Injection IP core. For more information, contact your local Intel FPGA sales representative.
- ...
- (Optional) FEATURE line in your Intel FPGA license that enables the Advanced SEU Detection IP core."
Regular ContributorCould you try with a empty design? I dont do any setting, just create a new design in new folder and i can see the option selectable.
New ContributorI created six different blank designs. In each scenario I followed the steps below:
- Open the Quartus Software
- Create a new project
- Select the part from the table below
- Did not add any source files
- Finish creating the project
- Return to Assignments > Device > Device and Pin Options > Error Detection CRC
- Record the options I have there
The table below shows the results.
| Quartus Version | Part | Result |
| Quartus Prime 16.0 Standard (licensed) | 10AXS2F45I1SG | Generate SMH file was greyed out (not selectable). The other options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by. |
| Quartus Prime 19.3 Pro (Licensed) | 10AXS2F45I1SG | Generate SMH file was not an option. The options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by. |
| Quartus Prime 19.3 Pro (Licensed) | 1SG280LU3F50E3XG | Generate SMH file was not an option. The options were enable error detection check, minimum SEU interval, enable internal scrubbing. |
| Quartus Prime 20.1.1 Standard (Licensed) | 10AXS2F45I1SG | Generate SMH file was greyed out (not selectable). The other options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by. |
| Quartus Prime 21.1 Pro (Licensed) | 10AXS2F45I1SG | Generate SMH file was not an option. The options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by. |
| Quartus Prime 21.1 Pro (Licensed) | 1SG280LU3F50E3XG | Generate SMH file was not an option. The options were enable error detection check, minimum SEU interval, enable internal scrubbing. |
These are all of the configurations I have tried. As you can see, I've tried on the Arria 10 and the Stratix 10 on many different versions (pro and standard) all of which were licensed. My license is a Quartus Prime Pro Fixed that expires in April 2022.
Any other thoughts? Is it possible that this feature is only supported on internal versions of Intel FPGA Quartus Prime? And the version that is released to the public does not have this capability?
