Forum Discussion
New ContributorOn-Chip Lookup Sensitivity Processing on Stratix10, Arria 10
Ok, it looks like the answer here is that you need FEATUREs in your license file in order to do the sensitivity processing. In the end I contacted the sales department, let them know what I wanted to do, and then they sent me a new license that had more FEATUREs in it.
Once you know this is the issue, you can actually see it in one of the user guides. There wasn't anything about it in the Advanced SEU Detecetion IP core guide, nothing in the Error Message Register Unloader IP core guide. However, there's a line in the Fault Injection IP core guide that says,
"The following hardware and software is required to use the Fault Injection Debugger:
- FEATURE line in your Intel FPGA license that enables the Fault Injection IP core. For more information, contact your local Intel FPGA sales representative.
- ...
- (Optional) FEATURE line in your Intel FPGA license that enables the Advanced SEU Detection IP core."
New ContributorBruce,
Thank you for pointing me that direction. I've looked at that document when trying to get the system working on the Stratix 10, but found that the Quartus Prime software wouldn't let me put in certain IP (i.e. the EMR register) into the design. It looks like the IP documentation contradicts itself in that regard. The Stratix 10 SEU mitigation user guide states that I should be able to use it, but the user guides for the individual IP state that the Stratix 10 is not supported. And my experience points to the fact that the Stratix 10 is not supported for several IP blocks.
Another issue I ran into was that in that user guide you referenced, it talks about using an SMH file. However, that option does not exist when I navigate to the Device and Pin Options menu. It's not that the checkbox isn't clickable, but doesn't exist altogether.
Do you by chance have an example design with this flow working that I could use to start from? Or do you have any answers to my questions asked above?
