on chip FIFO memory question

Thank you Steffen.

the PC hung up issue was fixed.

I use FIFO to transfer instruction from PC to endpoint.

so I need a siganl to inform FPGA that the commands have been wroten to FPGA.

then, FPGA fetch them command to do DMA process..

I want to use FIFO's interrupt signal (write port's, I export this singal from the Qsys core to my VHDL process).

so I set up the FIFO's REG (almostfull REG)=24(byte) & enable it's interupt REG.

the test result didn't meet my expection.

I also found if the status_REG's overflow bit or underflow bit is '1', this fifo will refuse to work either write data or read data.

the fill_level REG will always be zero.

what is the root cause?

Thank you in advance!