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Altera_Forum's avatar
Altera_Forum
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12 years ago

on chip FIFO memory question

Hello,

I met a question when add on-chip FIFO memory in Qsys.

when writing data to FIFO core, it can result in PC hung up.

pls see the attached file for details

would you please help me?

Thanks

13011010317

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You have the checkbox "Allow Backpressure" activated.Deactivate it or else a full FIFO tells your Computer to wait until there is space to write the data. And when the rest of your design doesn't empty the FIFO there will never be Space again .......

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thank you Steffen.

    the PC hung up issue was fixed.

    I use FIFO to transfer instruction from PC to endpoint.

    so I need a siganl to inform FPGA that the commands have been wroten to FPGA.

    then, FPGA fetch them command to do DMA process..

    I want to use FIFO's interrupt signal (write port's, I export this singal from the Qsys core to my VHDL process).

    so I set up the FIFO's REG (almostfull REG)=24(byte) & enable it's interupt REG.

    the test result didn't meet my expection.

    I also found if the status_REG's overflow bit or underflow bit is '1', this fifo will refuse to work either write data or read data.

    the fill_level REG will always be zero.

    what is the root cause?

    Thank you in advance!