On board USB Blaster?

I know many of the dev boards come with a built in usb-blaster that uses a Max family CPLD.

So the schematics are readily available. I haven't looked for the CPLD code, but I'm sure it's out there as well.

Pete

Unfortunately, the USB Blaster design can only be licensed from Altera and this includes the code which is in the MAX CPLD. The implementation in the standalone USB Blaster and the version embedded in the Development Kits is nearly identical.

I did hear of one company figuring out the protocol and creating their own, but this requires a considerable effort.

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I want to design in a USB Blaster type adaptor on my ARM board so I can test and program the entire system in situ. I have a spare USB port. It sounds like a good idea in principle but is there a reference design somewhere for this? Is the Altera USB Blaster design open source?

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There is no open-source USB-Blaster design. There is some information on the web on the protocol used over USB, but you also have to emulate the FTDI FT245 protocol, which is also undocumented. The undocumented protocols can be traced using Wireshark under Linux, however, there's no guarantee you will manage to decode to entire protocol. Even if you manage to decode most of the protocol and get something to work, Altera could require a Quartus update that subsequently breaks your reverse engineering and you'll have to start again (Apple have done this type of thing several times to stop you jailbreaking their phones).

If you don't care that Quartus cannot recognize your board, then your ARM micro can still be used to configure the FPGA and perform in-situ tests.

What functionality must you support?

Cheers,

Dave

Hi thanks for the input.

Quartus doesn't really matter - we just need to be able to use a JAM player or similar to program the system and perhaps run self tests etc.

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Quartus doesn't really matter

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Great, then that makes things a lot easier.

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we just need to be able to use a JAM player or similar to program the system and perhaps run self tests etc.

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Ok, then you'll be doing pretty much what I do.

Look at the schematic and various documents here:

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

For example, this doc discusses configuration and testing:

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)

Are you running Linux on your ARM processor? We run Linux on the PowerPC processor on the CARMA board. The MAX II devices on the board can only be programmed via JTAG, so we use a JAM Player port that runs on the x86 host PC, and accesses the JTAG chain via registers mapped to PCI. We did not bother to port it to the PowerPC, since the FPGA JTAG could be accessed with the PowerPC core held in reset. I don't think it would be too difficult to get it working on your ARM processor.

Since we also had the PowerPC JTAG port wired on the board, we let the JTAG programmer (BDI2000) take on some jobs, eg., programming the configuration flash, even though the FPGA could also have been used to perform that task (no point in duplicating effort though). Once the board is booted, the PCI interface can be used for reprogramming all devices on the board. The boards were manufactured with the MAX II devices and Flash programmed. Once they were booted in a compact PCI crate, the MAX II CPLDs were updated to the latest images using the Jam player, and the flash (with the SYS-FPGA, and PowerPC U-Boot images) was programmed.

Feel free to ask questions about the design.

Cheers,

Dave