OCT serial termination of Cyclone IV devices

Hi,
Rs OCT is implemented in Altera FPGA by selecting output transistors of different drive strength. LVDS IO standard is already using a specific drive strength selection (the lowest available), there's no option to further decrease it.

Drive strength of LVDS output correponds to 200 - 300 ohm Rs, adding e.g. 50 ohm would achieve little except for slightly reducing output current. To reduce slewrate, you can try small parallel capacitance of a few pF, either between differential lines or each line to ground. As 520 MBPS isn't much below maximal 700 MBPS LVDS rate, there is probably not much margin to slow down the signal without affecting reliability.

I appended Cyclone IV LVDS output characteristic (min, typ, max), extracted from IBIS file. I added a 220 ohm resistor curve for comparison.

Regards
Frank