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KBloo3's avatar
KBloo3
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1 year ago

OCT serial termination of Cyclone IV devices

Hi community, please, have a look at attached dokument "Cyclone_IV_OCT.pdf Table 6-2 Part 1 depicts different Rs OCT values in Ohms for several different I/O standards, single ended as well as diff...
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KBloo3's avatar
KBloo3
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1 year ago

Hi community,

please, have a look at my attached dokument.

So my question is:

Would it be possible to some how use the FPGA OCT feature or something else in the assignment editor in Quartus to achieve this thing inside the FPGA or must i change the pcb layout and put in 10 external resistors?

Best regards

Kenneth

FvM's avatar
FvM
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1 year ago
Hi,
your previous post asked about OCT Rs termination which isn't used or required for LVDS. Now you are referring to receiver Rd termination. Unfortunately it's not provided by Cyclone IV or Cyclone 10 LP FPGA series. LVDS receivers on Cyclone IV need external 100 differential termination. For a complete assessment, which device is driving LVDS, how long is the connection?
  • KBloo3's avatar
    KBloo3
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    1 year ago

    Hi,

    I described that in my attached file "Standard LVDS.pdf".

    The device driving LVDS (LVDS Tx) is a Dual Link LVDS Tx implemented in a Cyclone IV E FPGA. The receiver end (LVDS Rx) is a TFT display.

    The TFT display is terminated by 100 Ohm per differential pair.

    The total transmission line between FPGA and display consist of pcb traces from the FPGA to a LVDS connector and from the LVDS connector there is a twisted pair LVDS cable connected between the FPGA board connector and the display connector. The length of this transmission lines is about 25 cm and the speed of data is 520Mbps, so this transmission line must for sure be impedance balanced.

    This should be done by making single ended pcb traces impedance ~50 Ohm and differential impedance ~100 Ohm between each pair.

    When I analyzed the FPGA pcb board layout regarding routing the LVDS connections I found it to be a poor layout. LVDS pairs changing layers several times and at different places giving unnecessarily amount of via:s etc.

    All in all I think this poor layout, with so much impedance discontinuity, is the main root problem to the excessive EMI problem I have.

    My intention in this issue was to slow down the clock and data signals rise and fall time in the FPGA a litle bit to see if that can reduce the emission enough to make EMC accordance.

    So my question really was if I could set a OCT serial resistor value in the Cyclone IV E FPGA using the Quartus assignment editor or if I must put this resistors in the FPGA pcb layout?

    I hope I'm totaly correct intepreted now.

    Best regards

    Kenneth