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Altera_Forum
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14 years ago

object assigned a value but never read - does this effect synthesis?

Hello,

I have the following small module which is intended to store the value 0xFF in a register when a button is pressed. 


module connector_test(button, txd);
input button;
output reg txd;
reg  data;
always @(button) begin
    if(button==1'b0) begin
        txd <= 1'b0;
        data <= 8'hFF;
    end
    else begin
        txd <= 1'b1;
        data <= 8'b0;
    end
    
end
endmodule

I would expect the data register to be synthesized, but it seems to be completely disregarded and does not end up as part of the final circuit!

I get the following error during synthesis:

Warning (10036): Verilog HDL or VHDL warning at connector_test.v(5): object "data" assigned a value but never read

I'm not sure if the fact that the register is not read allows the synthesizer to assume that the logic is useless and automatically disregards it, or if something else is happening.

Any help in understanding this is appreciated!

-k

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    they just "work". How did you check for synthesis of the register?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes, I've looked at the other available attributes - and the only other that looks like it might apply is preserve - sadly, this didn't seem to work either.

    It looks like the noprune attribute is exactly what is needed in my case also, I'm not sure why it isn't responding to it.

    Do you recall having to do anything before using the attributes - or they just "work"?

    I also tried using type logic instead of reg as your have in your example - but this didn't change anything either.

    Any other suggestions?

    Thanks again!

    -k
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Here's what I've used: 

    
    // ------------------------------------------------------------
    // SignalTap II counter
    // ------------------------------------------------------------
    //
`ifdef USE_SIGNALTAP
    logic  count /* synthesis noprune */;
    always_ff @ (posedge clkin, negedge pcie_perstN)
    if (~pcie_perstN)
        count <= '0;
    else
        count <= count + 1;
`endif

    This preserves a counter that goes nowhere, which I can then probe with SignalTap ... which arguably means it goes somewhere ... however I needed to add this constraint so that Quartus would keep the counter so that I could probe it.

    There are a few other synthesis attributes; keep, preserve, etc. Try a few :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the reply - that's enlightening!

    Unfortunately, after adding the synthesis attribute, the register is still not synthesized.

    Is there a setting in Quartus that needs to be enabled so that synthesis attributes are not ignored - or am I simply using this incorrectly?

    The new code is below: 

    
module connector_test(button, txd);
input button;
output reg txd;
reg  data /* synthesis syn_noprune */;
always @(button) begin
    if(button==1'b0) begin
        txd <= 1'b0;
        data <= 8'hFF;
    end
    else begin
        txd <= 1'b1;
        data <= 8'b0;
    end
    
end
endmodule