Altera_Forum
Honored Contributor
16 years agoNovice JTAG test enquiry
Hi All
First post here.. hope this is the right place. I have accepted a design consultant post for a non-electronics company looking to modernise a system by migrating from discrete components to a Altera CPLDs. Part of my brief has also been to look into JTAG testing of the final circuits PCB for assembly errors. I have trawled the web-site but it is not immediately apparent how to do this. Can you use the STAPL language for example to set pin values via the device's JTAG registers ? Or are there simpler (low-cost) methods to acheive this. Advice or pointers on this aspect greatly appreciated. Paul ------------------------Update 11/11/09 ----------------------- Just came across this web-site offering Free JTAG stuff - www.jtaglive.com (http://www.jtaglive.com)