Not operational : clock skew > data delay

Hi,

Quartus classifies clocks as: Base or derived.

Base clock is the one connected to input clock pin.

Derived clocks are those generated from a base clock in a PLL or logic(gated).

for PLL derived clocks quartus generates clock settings.

For base or gated derived clock you need to enter the clock settings e.g. frequency so that timing analyser can give you correct results.

But first make your clock global then enter settings in the timing analyser.

kaz