Not operational : clock skew > data delay

Hi,

A clock source to fpga is either external and connected to fpga clock pin(This is global line) or a clock signal is generated internally by two methods:

1) PLL (again this becomes global)

2) from logic e.g. inversion or halving by flipflops or using counters...etc. Here Quartus wouldn't make it global always so you need to to go to:

assignment editor, select the clock signal and choose global.

kaz