non-application pin Model for Cyclone II

Is there something like a physical model, describing the behaviuor of such pins like Status, nConfig, MSEL and these ?

I am setting up a system to load and automatically reload FPGAs with new images from sources like e.g. flash. This whole process is a bit confusing, so I am using a simulation to check the timing. Bus behaviour is e.g. on topic: One ("big boss") FPGA loads data and moves it to the flash in chuncks and thus partly occupies the bus for short moments, another one uses flash data to configure FPGAs. All FPGAs use the same busses for data and addresses, so I am a bit concerned about the timeouts. For example, when do pins become active after configuration, and how quick do the switch intom tri state with a) nCE and nOE ?

I want to use such a model as a wrapper for my full design to have a complete toplevel simulation.

:o