Honored Contributor
Honored ContributorThe problem is what I said before: you don't have any synchronization signal.
When you start dma (tx) on PIO port A, the dma engine will transfer data from memory to pio at the fastest speed possible, depending from bus sharing and arbitration (up to a byte every clock cycle if the bus is not busy!!). Then, if your dma is 10 bytes long and you have 1 to 10 data in memory, you'll see those data byte values rapidly changing on PIO outputs. When you start rx dma on PIO port B, the tx dma has probably already ended, so you will get 10 times the same value, i.e. the last one driven. The same would happen with your FIFOs. You must provide a synchronization signal. How is your system supposed to signal FIFO to push/pop a single byte of data? Usually the external peripheral has address, chip select and rd/wr lines. Then, when you start a dma transfer, these signals changing at every dma access will tell the peripheral to modify the driven/latched data. I hope my explanation is clear to you Cris
