Forum Discussion
Altera_Forum
Honored Contributor
14 years agonios2-flash-programmer : elf & sof
Hi all
I have a zImage that uses SDRAM. this Image contains an application to configure the ethernet (a default IP address 192.168.10.180) and starts a TCP server when I use nios2 shell: nios2-download-g zImage & nios2-terminal it works well and the application set to launch at startup is working properly (ping 192.168.10.180 => ok) Now i need to enable the system to start from power on so I - from quartus i use " convert programming files " to program .jic file in EPCS16 ==> OK II - zImage into cfi flash ( base = 0x02800000 End = 0x02FFFFFF) 1- in SOPC, jtag_uart: NO_interactive_windows and nios_cpu reset vector 0x02800000 2- elf2flash - base = 0x02800000 - end = 0x02FFFFFF - reset = 0x02800000 - input = zImage - output = uc_flash.flash - boot = / cygdrive/e/01_Application/Altera/nios2eds/components/altera_nios2/boot_loader_cfi . srec ==> OK 3-nios2-flash-programmer --base=0x02800000 uc_flash.flash ==> download ok , checksum ok, leaving target processor paused When I reboot and I ping 192.168.10.180 nothing happens. I don't know if I missed a step!!! thanks for help11 Replies
- Altera_Forum
Honored Contributor
You've described what you're doing with your software image, but where is your hardware image (FPGA programming file/SOF) being stored?
If it's also in the EPCS, then what you're attempting to do won't work....to the best of my knowledge. The default bootloader for EPCS expects to see a SOF with an ELF immediately following it in the EPCS device... It may also work with just the ELF being stored in the EPCS, but I haven't tried that. You CAN do what you'd like to do, using some sort of dual bootloader scheme, but you have to understand that by pointing the processor's reset address to the EPCS device you are telling the processor to run the small bootloader that resides on an onchip memory that is a part of the epcs_controller component. Cheers! slacker