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Altera_Forum
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15 years ago

nios II processor interface with memory

Hi, How do we connect three different memories to niosII processor so that we can access these three memories independently.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

thread bump: hope this is okay ?

The "my_custom_vhdl_Base_adr" found in system.h on the nios side, provides an adr for "my_custom_vhdl" block so i can IOWR/IORD, to it from nios, but if i want to write(to some place in the onchip ram) from "my_custom_vhdl" and read(from some place in the on chip ram) from nios, how do you map that i Qsys and what VHDL would you use ?

/thanks in advance