NIOS II do not run

Hi,

Have you specified which mem area the nios cpu goes after reset?

Both in the SOPC and the bsd editor?

And, Nios hangs when you use stdio like printf and don't connect the blaster.

So set stdio to null in the bsd editor.

apus

Hi Agdepus,

thanks fpr your reply.Here is my code:

# include "sys/alt_stdio.h"# include <system.h># include "altera_avalon_pio_regs.h"# include "alt_types.h"# include "string.h"# include "math.h"
int main () {
  while(1){
    IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, 1);
   }
    return 0;
}

I have still some libs included I need for later use. Is this a problem?

The reset_vector in the SOPC-system I have set but what is the BSD-Editor?I only know the BSP-Editor. Where can I find the BSD-Editor and where can I set stdout to NULL?

Is ist a special problem, when I allocate as followed:

add_section_mapping .text cfi_flash_0

add_section_mapping .rodata cfi_flash_0

add_section_mapping .exceptions onchip_memory2_0

add_section_mapping .rwdata onchip_memory2_0

add_section_mapping .bss onchip_memory2_0

???

It would be nice to get help! Thanks again!

Steffen

Hi,

you'll find the bsp editor if you rigth click on the syslib project in Nios EDS.

You should also remove support for c++.

And we normally point the .exceptions to the program memory. Unless you have code to handle it.

apus

--- Quote Start ---

I saved the .sof and .elf file in a 16MB-flash.

--- Quote End ---

Maybe it is a silly question, but is it really possible to use a *.sof file for a flash? I thought it must be a *.pof or *.jic-file to work after power-up.

Or is it a spelling mistake?

Philipp

Hi,

the sof cannot be saved to flash.

If you use a Blaster you should generate a JIC file and use that.

There are numerous ways to do this, and i wonder how you manage to program the flash with a sof file...do you use an external programmer?

If you are using a small program then you may use the internal ram in the fpga as code storage.

Like 20K ROM and 8K ram should work fine (actually much smaller if you have to).

Whe you generate your nios files you must:

-- Set stdio away from the jtag_uart (maybe a RS422/RS232 output port is available)

-- Map the different locations to rom and ram (and the cpu reset vector)

-- Turn off c++ support and exit support

After compilation:

- Update the .hex files in the quartus directory (Nios)

- Update mem init files (quartus)

- Run assembler (quartus)

Convert sof to Jic.

Program EPCS (or other flash)

Now you code is embedded in the internal ram of the fpga.

With some luck your program will run from flash.

(Note that there are other issues you will need to address, but this is a rough roadmap)

Once it is running you can start porting the whole project to flash.

Apus

Hi,

it is working now. The solution was to disable stdout. The .sof is saved on the flash. A CPLD is configuring the FPGA when power comes up.

Thanks for your helpful answers!!!

Cheers Steffen

Hi,

I have no experience with CPLD flash controllers and external flash, so great!!

apus