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You can probably just put the boot code into a user-defined internal memory block, and point the nios reset vector at it.
That would remove the problems of the sopc builder repeatedly substituting its own file.
After all, I presume that is what happens anyway.
It would also let you use TCM for the boot code (probably more useful for the JTAG block though since you are probably copying code to SDRAM and have an instruction cache anyway).
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Dsl,
I am following what you suggested. My problem is that the EPCS controller does not give me a transmit ready signal (when I read the status register)and the bootloader gets stuck in the loop waiting for the flash to be ready. If you look at the object file dump,
// Wait until controller is ready for a TX-char, then send it.
tx_ready_loop:
ldwio rf_temp, EPCS_STATUS_OFFSET (r_epcs_base_address)
d0: 92400237 ldwio r9,8(r18)
andi rf_temp, rf_temp, EPCS_STATUS_TRDY_MASK
d4: 4a40100c andi r9,r9,64
beq rf_temp, r_zero, tx_ready_loop
d8: 483ffd26 beq r9,zero,d0 <tx_ready_loop>
stwio r_epcs_tx_value, EPCS_TXDATA_OFFSET (r_epcs_base_address)
dc: 92c00135 stwio r11,4(r18)
It is here where I am not able to move forward. I never get reach address 0xdc.
Till this point I am fine.
This is my flow
I keep the bootloader on internal memory and upon finding that the boot is for application image, I load the bootloader to an on-chip ram.
I reset the nios control to the bootlader and let it run. When i am debugging the bootloader (i access the on-chip memory and put return instruction at various location to see how far the flow runs), I get stuck in the above loop shown.
Any help would be great.
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