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Altera_Forum
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10 years ago

Nios Boot up from EPCS

I am having trouble booting up my Nios C code from EPCS. I am building my own FPGA board, not using a demo board. Here are the steps I am following:

1) In Qsys define nios ii reset vector to epcs_flash_controller with 0 offset. define expection vector as on chip ram.

2) generate SOF file in Quartus

3) generate ELF file in NIOS IDE

4) generate hw.flash and sw.flash files using Nios Flash programmer GUI

5) convert my sw.flash into sw.hex in NIOS terminal using the following command:

nios2-elf-objcopy --input-target srec --output-target ihex "sw.flash" "sw.hex"

6) Using Convert Progamming Files in Quartus I create a pof file:

6a) Select EPCS128 (that is the flash chip i'm using)

6b) Advanced > Disable EPCS ID check

6c) Add SOF Page -> Page 0 -> Properties -> Address mode for selected pages: Set to START and Start Address = 0x0

6d) Add file to SOF page: Add hw.sof

6e) Properties of hw.sof select Compression

6f) Add HEX data

6g) Add File -> sw.hex

6h) Use Relative addressing offset 0x1. If I use Absolute my hex and sof files overlap.

Right now, the hex file should follow the sof file in the flash addresses

7) Generate POF file -> NO issues.

8) Program EPCS device using Active Serial Programming. Add my POF file. Programming succesful.

9) Power cycle my board. The hardware file starts, but the NIOS never boots?

So what is going wrong? I am programming using the USB Blaster that Altera sells. I am also not going through JTAG. I am first programming the EPCS chip. Then turning off power and disconnecting the programming cable. Then I repower the board. As# 9 says, the hardware file starts but my NIOS doesn't seem to run the sw.hex code.

Any ideas?

Thanks

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More info:

I tried programming via JTAG cable like one would normally do on a demo board.

1) Upload SOF to FPGA

2) Upload ELF in NIOS IDE via Run Configurations

In this case the NIOS code works as expected.

Then I tried using the Flash Programmer to write the hw.flash and sw.flash files to the EPCS via the JTAG chain. In the GUI I got no errors. Code supposedly uploaded to the flash chip with out issues.

Upon re-powering up, I expect the FPGA to be configured from the EPCS device. Just like before, the NIOS never boots.

So clearly there is some issue with the FPGA bootloader and how it interprets the sw.hex or sw.flash file on the EPCS flash chip....

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    OK. Here is my solution.

    Instead of generating a pof file I generated a jic file in Convert Programming Files. Here you can select you target FPGA device and target flash/epcs device. The main point is to NOT compress the SOF file. However, when you do this, the sw.hex relative address is no longer 0x1. To find this value I first tried to generate with the improper offset. This produces an error that tells the address space of the sof file. Then you can adjust the sw.hex file address to be 1 byte after the uncompressed sof file.

    The JIC file is programmed in JTAG mode instead of the sof file. (I have yet to try this same uncompressed trick with a pof file).

    Now the FPGA will be configured from the EPCS flash on power up of the board.

    Why this complete method of configuring the EPCS device and the FPGA is so convoluted, is a mystery to me. It seems like such a crucial process should be well streamlined....

    So in summary if you follow all the steps EXCEPT for step 6e --> do not compress the sof, and if you manually set up the address space for the hex file properly, then the configuration process and nios boot up will work properly.