Forum Discussion

drecassiano's avatar
drecassiano
Icon for New Contributor rankNew Contributor
3 years ago

NIOS 2 Development: Compile

I create a NIOS 2 processor in platform designer 18.1 and then transferred into a Verilog file and then I do the following below in Quartus prime lite edition18.1. (double click) core(dir) (sel...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Do you have any further update or concern?


Thanks,

Sheng


drecassiano's avatar
drecassiano
Icon for New Contributor rankNew Contributor
3 years ago

Thanks for the reply. I have tried adding the core.qsys with the DE10_LITE_Golden_Top Verilog as can be seen below but still no luck as the following error messages get shown when compilation is finished. Let me know if anyone knows the solution?