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drecassiano
New Contributor
New ContributorNIOS 2 Development: Compile
I create a NIOS 2 processor in platform designer 18.1 and then transferred into a Verilog file and then I do the following below in Quartus prime lite edition18.1.
(double click) core(dir)
(sel...
sstrell
Super Contributor
Super ContributorDid you add the .qip or .qsys file to your Quartus project (Project menu -> Add/Remove files in project)? Either way, your PD system file must be named core.qsys. core.qip will not be created unless you manually generate your PD system, so it's usually easier to just add the .qsys file to your project so the system gets generated every time you compile your project.
drecassianoNew Contributor
New ContributorThanks for the reply. I have tried adding the core.qsys with the DE10_LITE_Golden_Top Verilog as can be seen below but still no luck as the following error messages get shown when compilation is finished. Let me know if anyone knows the solution?
