Nichestack Tutorial Using Arria V GX starter board

And ted,

I am currently trying to use SignalTap with my design. I am looking for the Avalon ST ports you mentioned, and the ports I have monitored so far are (as defined in my system) enet_rx_d[3:0], enet_tx_d[3:0] (which are ports in the verilog file), and then also ports from the qsys files; the sgdma_tx and sgdma_rx (specifically out start_of_packet/end_of_packet and in start_of_packet/end_of_packet, respectively). Do these seem like the right signals? I figured since were trying to see if anything is recieved/sent by the board that these would be a good place to start.

I'm also trying to figure out how to set up the trigger for this application... I need to be careful as these are 25 min+ compiles. I ran it without setting up the trigger and the outputs were enet_rx_d[3:0] = 0100 and enet_tx_d[3:0] = 0000 constantly (but this is probably bad data)

P.S. If it would help to send parts of my design for reference (qsys files, verilog files) that is another possibility just let me know.

EDIT: After running signal tap with the help of a colleague, it appears to me that the FPGA is not recognizing any incoming signals from the ethernet cable, and therefore does not even know to send data back. Looking in more on where to start on this issue tomorrow morning.