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Altera_Forum's avatar
Altera_Forum
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15 years ago

Newbie help required ref MAX II

Hi Everyone

I'm a complete newbie when it comes to CPLD's.

I've been programming PIC's for years but CPLD's are new to me and i would very much appreciate some help to get me started, thank you :)

Here's me questions :

1. My first question is regarding the CLK.

I mainly wish to use a MAX II as a multiplexer, routing 8 bit wide data signals to and from each other, basically sending 8 bits from here to there and then form here to over there and so on, from inputs to outputs and visa versa.

The data signals will be changing state at a speed of 16Mhz but the signals will only be fowarded through the Max II to assigned outputs.

Do i need to CLK the max II to do this?

If not, would i need a CLK if i was to store data at an output latch?

2. My second question is regarding a counter :

I need to create a 20 bit wide syncronous binary counter to address some sram.

The CLK speed will be 16Mhz max.

Do i inject this CLK signal into a simple assigned input pin or would it be better to inject this signal into the dedicated CLK inputs on the Max II?

The CLK signal will be in bursts and the idea is to code the program to count when it see's the clk signal.

3. Third and final question :

Lets say i have 8 bits connected to 8 assigned inputs, can i send these 8 bits to any assigned output pins on any bank or is it more complicated than that?

I apologise for all the questions but after reading the literature some for days now, i just cannot find the answers to the above.

Using the Max II as a multiplexer to just route signals looks simple but thought i'd ask the true experts :)

Many thanks for your time.

RonUK

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Question 1:

    You don't need a clock if you're just going to use combinatory logic or assynchronous sequential logic (latches).

    But problably you'll be unable to meet the timmings of your 16 MHz bus with just combinatory logic. Latches are supported but... I don't any experience with designing with latches but the general consensus is to avoid them as much as possible, at least in FPGAs/CPLDs.

    You should use synchronous logic (ie, registers) as much as possible. And for those, you need a proper clock signal.

    I presume your 16 MHz bus has an associated clock, I suggest you use it.

    2. As much as possible, use the dedicated clock pins for clocks. This way, the clock signal can be routed though the FPGA using the low skew global networks.

    3. There are no restrictions there.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you rbugalho & All.

    Your reply was very helpful.

    regarding simple logic configuration, here's a better example of my needs :

    The MAX II will be configured to have 10 inputs and 32 outputs for this project.

    The inputs will be used for 8 bits of data and 2 bits of control data.

    The outputs will be used as 4 x 8 bit outputs.

    When the two control inputs are "00" the signal present at the 8 data inputs must appear at outputs 1 to 8.

    When the two control inputs are "01" the signal present at the 8 data inputs must appear at outputs 9 to 16.

    When the two control inputs are "10" the signal present at the 8 data inputs must appear at outputs 17 to 24.

    When the two control inputs are "11" the signal present at the 8 data inputs must appear at outputs 25 to 32.

    As you can see, i'm just sending 8 inputs to 4 x 8 bit outputs.

    What would be a typical input to output delay for this configuration on the understanding that i'm not latching anything?

    Thanks again

    RonUK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    That will depend on the device (speed grade, size, etc), pin placement and how much logic you put in the path.

    I did a few quick experiments and got 10-13 ns.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi rbugalho

    Many thanks for checking the speed.

    10 - 13ns, not bad really.

    I'm currently putting together a developement board and looking forward in getting to grips with these superb chips.

    Thanks for your advice

    RonUK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    So, what are the other 24 outputs doing when they are not being selected by the control inputs?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jake :)

    The other 24 will be doing nothing, its simply a learning setup.

    I will be configuring different examples to test the device and learn it.

    I was a bit shocked to learn the Max & Max 2 devices can only be programmed 100 times!!

    What would be a better device to leatn with that has 100 pins, external sram and similar to the Max series?

    I would very much appreciate it if someone could link me to a schematic which shows the connections and setup of an Altera device with the external sram connections.

    Many thanks

    RonUK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes, the 100 writes limit is a bit unfortunate.

    The reasoning is, I think, that MAX II are very very optimized for volume.

    For on-off applications, such as development setup, the price diference between a MAX II and a small Cyclone is negligible.

    My choice would go to a Cyclone IV or III.

    Note however that these devices need several voltages: 1/1.2, 2.5 and 3/3.3V are a given.

    These devices are more flexible but also provide more ways to end up with a PCB design that doesn't work (this isn't meant to scare you).

    Recommended readings to avoid this annoying part:

    http://www.altera.com/literature/hb/qts/qts_qii52013.pdf

    http://www.altera.com/literature/an/an592.pdf

    http://www.altera.com/literature/dp/cyclone-iv/pcg-01008.pdf

    They also support several configuration schemes. For your application, I recommend the Active Serial + JTAG scheme. More information, including the schematics:

    http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf

    As a foreword, when reading the documentation, you'll probably come to conclusion that you need to pin headers for the programming cable: one to access the EPCS via the Active Serial and another to access the FPGA via JTAG.

    This is not quite true: you can do without a pin header in the AS interface and access the EPCS via JTAG through the FPGA, using the Serial Flash Loader function.

    This is a bit slower than direct acess and requires an extra step when generating the programming file but it works very well.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks rbugalho

    Phew!, i have some serious reading to do.

    The links are very helpful.

    Many thanks

    RonUK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi rbugalho

    The links were indeed VERY helpful!

    Please look at the image below, this looks to be the perfect option and in AS mode as you mentioned.

    http://www.sola-larm.com/cycloneconfig.jpg

    So with this configuration i just download from the PC via JTAG connector where the configuation program is stored in say an EPCS4SI8N device.

    After that if power is ever connected to the circuit the configuration program is automatically loaded into the Cyclone from the EPCS4SI8N IC.

    Please correct me if i'm wrong but its no different than programming a MAX device directly but the program storage is external. The MAX would require the JTAG method and the Cyclone the AS method of programming.

    1. Is the above configuration a standard and most used method?

    2. For developement, the Cyclone III (EP3C5) looks a good IC to learn with.

    After looking all over the Altera website, i can only find the pinout text for this device, not an actual diagram of the TQFP144 ic itself showing the pins like the MAX II PDF's which are superb!

    Can you advise a link to a diagram for the EP3C5 please?

    Things are coming together now, gradually clicking into place :).

    Many thanks

    RonUK

    P.S

    Your comments on the Cyclone voltage was also very helpful, when looking at the EP3C5 device it look pretty simple and as follows :

    Internal Logic (VCCINT) = 1.8v

    Digital Voltage for PLL (VCCD-PLL) = 1.8v

    Output Buffers (VCCIO) = 3.3v

    Analogue Voltage for PLL (VCCA) = 3.3v

    .
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    That diagram is just the AS part.

    It allows:

    a) the FGPA to load it's configuration on from the EPCS on power on

    b) you to read/write the EPCS' contents using the programmer cable

    c) allows the FPGA to read/write the EPCS' contents

    You need this circurtry, since you really want "a)". However, I'd also put in the JTAG circuitry.

    This allows you to, using the programming cable

    a) load a new configuration into the FPGA without writing the EPCS (much faster)

    b) use SignalTap to inspect signals within the FPGA

    c) read/write the EPCS' contents though the FPGA, using the SFL

    d) etc

    As for voltages, the EP3C5 is a member of the "Cyclone III" family, not the "Cyclone" family. Take some care, because there are substantial differences between the 4 Cyclone families.

    For Cyclone III, it's voltages are:

    - VCCINT: 1.2V

    - PLL VCCD: 1.2 V

    - PLL VCCA: 2.5 V

    - VCCIOs: 3.3V, if you want 3.3V TTL/CMOS I/Os

    Anyway, all of this needs to be double-checked against the guidelines and the .pin file that is produced by synthesis and against the pin connection guidelines:

    http://www.altera.com/literature/lit-dpcg.jsp

    As for packages,

    you can find a list of all packages used by Altera at http://www.altera.com/literature/ds/dspkg.pdf

    But what you problably want is to take a look at your schematic/pcb design tool's libraries.

    The most common ones will either include libraries for all Altera devices or you can find libraries for the latest Altera devices

    https://www.altera.com/support/software/download/sof-download_center.html