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Altera_Forum
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18 years ago

Newbie Help Request CPLD MAXII

Hi all. I want to build a digital clock, with several 7 segments displays (HH:mm:ss). How can i make the 1s clock to drive my 4bits counters? My board has a 50Mhz clock. How can i make 1s pre...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for your reply,

I've already typed my first verilog program :)

What do you think about this?

module clk1s (CLOCK_50,LED);

input CLOCK_50;

output LED;

reg LED;

integer count;

wire CLOCK_50;

always @ (posedge CLOCK_50)

begin

count = count + 1;

if (count >= 50000000)begin

LED = ~LED;

count = 0;

end

end

endmodule

Is there a simplest/better solution?

Regards