Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Newb question- If statements

Im new to programming in VHDL and I seem to be having some difficulty with a particular set of if statements. I understand how conditional statements work, but for whatever reason Im not getting the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

there are no pre-existing functions, because thats for you to generate and determine. Clock enables are more reliable because there is no worry about timing or temperature changes: 


process(clk)
begin
  if rising_edge(clk) then 
    if cnt = 999 then
      clk_en <= '1';
      cnt <= 0;
    else
      clk_cnt <= '0';
      cnt <= cnt + 1;
    end if;
    if clk_en = '1' then
      --do something every 1000 clocks
    end if;
  end if;
end process;