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Altera_Forum
Honored Contributor
Honored ContributorNewb question- If statements
Im new to programming in VHDL and I seem to be having some difficulty with a particular set of if statements. I understand how conditional statements work, but for whatever reason Im not getting the ...
Altera_ForumHonored Contributor
Honored Contributoryou may try something like:
process(rst, clk) begin if ( rsr = '0' ) then cnt_reg <= ( others => '0' ); elsif ( clk'event and clk = '1' ) then cnt_reg <= cnt_next; end if; end process; cnt_next <= cnt_reg + 1 when ( cnt_reg < 81000000 ) else ( others => '0' ); process(cnt_reg) begin IF(cnt_reg = 81000000)THEN clkout <= '0'; ELSIF(cnt_reg = 27000000)THEN clkout <= '0'; ELSIF(cnt_reg = 54000000)THEN clkout <= '1'; ELSE clkout <= '1'; END IF; end process;
