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Altera_Forum
Honored Contributor
Honored ContributorNew to VHDL: Understanding timer.vhd implementation
I'm an old hand at C/C++ just getting my feet wet with VHDL. In the course of my learning, I've used the SOPC builder to create a simplified system that included a timer. Part of the emitted VHDL c...
Altera_ForumHonored Contributor
Honored ContributorUnderstandable. I was just answering your question about why std_logic'() was being used all over the place...
I also wanted to make sure there wasn't anything I wasn't "getting" with respect to clk_en usage. Thanks for all the help! --tim
